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1 ltc3730 3730fa , ltc and lt are registered trademarks of linear technology corporation. burst mode, opti-loop and polyphase are registered trademarks of linear technology corporation. stage shedding is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5481178, 5929620, 6177787, 6144194, 6100678, 5408150, 6580258, 6462525, 6304066, 5705919. features applicatio s u typical applicatio u 3-phase, 5-bit intel mobile vid, 600khz, synchronous buck controller the ltc ? 3730 is a polyphase ? synchronous step-down switching regulator controller that drives all n-channel external power mosfet stages in a phase-lockable fixed frequency architecture. the 3-phase controller drives its output stages with 120 phase separation at frequencies of up to 600khz per phase to minimize the rms losses in both the input and output filter capacitors. the 3-phase tech- nique effectively triples the fundamental frequency, im- proving transient response while operating each controller at an optimal frequency for efficiency and ease of thermal design. light load efficiency is optimized by using a choice of output stage shedding or burst mode technology. an internal operational amplifier provides mode selectable output voltage programming in conjunction with the inter- nal vid voltage control dac. soft-start and a defeatable, timed short-circuit shutdown protect the mosfets and the load. current foldback provides protection for the external mosfets under short-circuit or overload conditions. 3-phase current mode controller with onboard mosfet drivers 5% output current match optimizes thermal performance and size of inductors and mosfets operational amplifier accomodates mode switching 1% v ref accuracy over temperature reduced input and output capacitance reduced power supply induced noise v out programmable from 0.6v to 1.75v (imvp iii) 10% power good output indicator 250khz to 600khz per phase, pll, fixed frequency pwm, stage shedding tm or burst mode ? operation opti-loop ? compensation minimizes c out adjustable soft-start current ramping 4v, v in , undervoltage run/ss reset/reattempt circuit short-circuit shutdown timer with defeat option overvoltage soft latch small 36-lead narrow (0.209) ssop package tablet computers high performance notebook computers high output current dc/dc power supplies figure 1. high current triple phase step-down converter 0.003 ? 1 h 22 f 35v 0.003 ? 1 h v in 0.003 ? c out 470 f x4 2.5v v out 1.2v 50a v in 5v to 28v 1 h v in 3730 f01 tg1 v cc 0.1 f sw3 sw2 sw1 sw1 bg1 sense1 + sense1 C boost1 boost2 boost3 tg2 sw2 bg2 pgood pllin pllfltr i th 0.1 f 100pf 680pf 5 vid bits 5k optional sync in power good indicator run/ss sgnd eain ampout pgnd vid0-vid4 sense2 + sense2 C tg3 sw3 bg3 sense3 + sense3 C in C in + + 10 f v cc 4.5v to 7v + ltc3730 descriptio u
2 ltc3730 3730fa absolute axi u rati gs w ww u package/order i for atio uu w electrical characteristics (note 1) topside driver voltage (boost n ) range .. 38v to C0.3v switch voltage (sw n ) range ........................ 32v to C5v boosted driver voltage (boost n C sw n ) .... 7v to C0.3v peak output current <1ms (tg n , bg n ) ..................... 5a supply voltage (v cc ), pgood pin voltage range ....................................... 7v to C0.3v pllin, run/ss, pllfltr, fcb voltages .. v cc to C0.3v i th voltage range ..................................... 2.4v to C0.3v operating ambient temperature range ....... 0 c to 70 c junction temperature (notes 2, 7) ....................... 125 c storage temperature range ..................C65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number ltc3730cg 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 top view g package 36-lead plastic ssop 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 vid1 pllin pllfltr fcb in + in C ampout eain sgnd sense1 + sense1 C sense2 + sense2 C sense3 C sense3 + run/ss i th vid2 vid0 pgood boost1 tg1 sw1 boost2 tg2 sw2 v cc bg1 pgnd bg2 bg3 sw3 tg3 boost3 vid4 vid3 t jmax = 125 c, ja = 95 c/w consult ltc marketing for parts specified with wider operating temperature ranges. the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = v run/ss = 5v unless otherwise noted. symbol parameter conditions min typ max units main control loop v regulated regulated voltage at in + (note 3); vid code = 11111, v ith = 1.2v 0.596 0.600 0.604 v 0.594 0.600 0.606 v v sensemax maximum current sense threshold v eain = 0.5v, v ith open, 65 75 85 mv v sense1 C , v sense2 C , v sense3 C = 0.6v, 1.8v 62 75 88 mv i match maximum current threshold match worst-case error at v sense(max) C5 5 % v loadreg output voltage load regulation (note 3) measured in servo loop, ? i th voltage = 1.2v to 0.7v 0.1 0.5 % measured in servo loop, ? i th voltage = 1.2v to 2v C0.1 C0.5 % v reflnreg output voltage line regulation v cc = 4.5v to 7v 0.03 %/v g m transconductance amplifier g m i th = 1.2v, sink/source 25 a (note 3) 3.6 5 6.6 mmho g mol transconductance amplifier gbw i th = 1.2v, (g m ? z l , z l = series 1k-100k ? -1nf) 3 mhz v fcb forced continuous threshold 0.58 0.60 0.62 v i fcb fcb bias current v fcb = 0.65v 0.2 0.7 a v binhibit burst inhibit threshold measured at fcb pin v cc C 1.5 v cc C 0.7 v cc C 0.3 v uvr undervoltage run/ss reset v cc lowered until the run/ss pin is pulled low 3.2 3.8 4.5 v order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/
3 ltc3730 3730fa electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = v run/ss = 5v unless otherwise noted. symbol parameter conditions min typ max units i q input dc supply current (note 4) normal mode v cc = 5v 2.3 3.5 ma shutdown v run/ss = 0v, vid0 to vid4 open 20 50 a i run/ss soft-start charge current v run/ss = 1.9v C0.8 C1.5 C2.5 a v run/ss run/ss pin on threshold v run/ss , ramping positive 1 1.5 1.9 v v run/ssarm run/ss pin arming threshold v run/ss , ramping positive until short-circuit 3.8 4.5 v latch-off is armed v run/sslo run/ss pin latch-off threshold v run/ss , ramping negative 3.2 v i scl run/ss discharge current soft-short condition v eain = 0.375v, v run/ss = 4.5v C5 C1.5 a i sdlho shutdown latch disable current v eain = 0.375v, v run/ss = 4.5v 1.5 5 a i sense sense pins source current sense1 + , sense1 C , sense2 + , sense2 C ,1320 a sense3 + , sense3 C all equal 1.2v; current at each pin df max maximum duty factor in dropout, v sensemax 30mv 95 98.5 % tg t r, t f top gate rise time c load = 3300pf 30 90 ns top gate fall time c load = 3300pf 40 90 ns bg t r, t f bottom gate rise time c load = 3300pf 30 90 ns bottom gate fall time c load = 3300pf 20 90 ns tg/bg t 1d top gate off to bottom gate on delay all controllers, c load = 3300pf each driver 50 ns synchronous switch-on delay time bg/tg t 2d bottom gate off to top gate on delay all controllers, c load = 3300pf each driver 60 ns top switch-on delay time t on(min) minimum on-time tested with a square wave (note 5) 110 ns vid parameters vid il maximum low level input voltage 0.4 v vid ih minimum high level input voltage 2 v vid pullup vid0 to vid4 internal pull-up current v vid = 0v 3 a atten err vid0 to vid4 (note 6) C 0.25 0.25 % power good output indication v pgl pgood voltage output low i pgood = 2ma 0.1 0.3 v i pgood pgood output leakage v pgood = 5v 1 a pgood trip thesholds v ampout with respect to set output voltage, v pgthneg v ampout ramping negative vid code = 11111, C7 C10 C13 % v pgthpos v ampout ramping positive pgood goes low after v uvdly delay 7 11 13 % v uvdly power good fault report delay after v eain is forced outside v uv threshold 100 150 s oscillator and phase-locked loop f nom nominal frequency v pllfltr = 1.2v 360 400 440 khz f low lowest frequency v pllfltr = 0v 190 225 260 khz f high highest frequency v pllfltr = 2.4v 600 680 750 khz r pllth pllin input threshold 1v r pll in pllin input resistance 50 k ? i pll lpf phase detector output current sinking capability f pllin < f osc 20 a sourcing capability f pllin > f osc 20 a r relphs controller 2-controller 1 phase 120 deg controller 3-controller 1 phase 240 deg
4 ltc3730 3730fa electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = v run/ss = 5v unless otherwise noted. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. a maximum current of 200 a is allowed to pull up the run/ss pin to prevent overcurrent shutdown. note 2: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: ltc3730cg: t j = t a + (p d 95 c/w) note 3: the ic is tested in a feedback loop that includes the operational amplifier in a unity-gain configuration loaded with 100 a to ground driving the vid dac into the error amplifier and servoing the resultant voltage to the midrange point for the error amplifier (v ith = 1.2v). note 4: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see applications information. note 5: the minimum on-time condition corresponds to an inductor peak- to-peak ripple current of 40% of i max (see minimum on-time considerations in the applications information section). note 6: the atten err specification is in addition to the output voltage accuracy specified at vid code = 11111. note 7: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125 c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. symbol parameter conditions min typ max units operational amplifier i b input bias current 15 200 na v os input offset voltage magnitude in + = in C = 1.2v, i out = 1ma 0.8 5 mv cm common mode input voltage range 0 v cc C 1.4 v cmrr common mode rejection ratio i out = 1ma 46 70 db i cl output source current 10 35 ma a vol open-loop dc gain i out = 1ma 30 v/ v gbp gain bandwidth product i out = 1ma 2 mhz sr slew rate r l = 2k 5 v/ s v o(max) maximum high output voltage i out = 1ma v cc C 1.2 v cc C 0.9 v overtemperature shutdown t shdn temperature shutdown temperature rising 130 165 c
5 ltc3730 3730fa efficiency ( % ) 0.1 load current (a) 100 90 80 70 60 50 40 30 20 10 0 1 10 100 3730 g01 v in (v) 0 efficiency (%) 100 95 90 85 80 75 70 65 60 55 50 20 3730 g02 5 10 15 25 frequency (khz) 200 efficiency (%) 100 95 90 85 80 75 600 3730 g03 300 400 500 temperature ( c) C50 reference voltage (mv) 110 3730 g04 C10 30 70 610 605 600 595 590 C30 10 50 90 temperature ( c) C45 4.0 error amplifier g m (mmho) 4.5 5.5 6.0 C15 15 30 90 3730 g05 5.0 C30 0 45 60 75 temperature ( c) C45 C15 15 30 90 3730 g06 C30 0 45 60 75 maximum i sense threshold (mv) 85 80 75 70 65 temperature ( c) frequency (khz) 700 600 500 400 300 200 100 0 3730 g07 C45 C15 15 30 90 C30 0 45 60 75 temperature ( c) 3730 g09 C45 C15 15 30 90 C30 0 45 60 75 3730 g08 0 under voltage reset (v) 1 3 4 5 2 v in = 8v v out = 1.5v i load = 20a v out = 1.5v v fcb = open v fcb = 5v v fcb = 0v i out = 45a i out = 15a v out = 1.5v f = 250khz v in = 20v v in = 12v v in = 8v v in = 5v v o = 1.75v v o = 0.6v v pllfltr = 2.4v v pllfltr = 1.2v v pllfltr = 0v v pllfltr = 5v pllfltr pin voltage (v) 0 oscillator frequency (khz) 700 600 500 400 300 200 0.5 1 1.5 2 2.5 typical perfor a ce characteristics uw efficiency vs i out (figure 14) efficiency vs v in (figure 14) efficiency vs frequency (figure 14) reference voltage vs temperature error amplifier gm vs temperature maximum i sense threshold vs temperature oscillator frequency vs temperature oscillator frequency vs v pllfltr undervoltage reset voltage vs temperature
6 ltc3730 3730fa 0 run/ss pin voltage (v) 1 3 4 5 2 0 run/ss pullup current ( a) 0.5 1.5 2.0 2.5 1.0 0 supply current (ma) shutdown current ( a) 0.4 2.0 1.6 2.4 2.8 1.2 0.8 temperature ( c) 3730 g10 C45 C15 15 30 90 C30 0 45 60 75 90 maximum duty factor (%) 92 96 98 100 94 temperature ( c) 3730 g16 C45 C15 15 30 90 C30 0 45 60 75 temperature ( c) 3730 g11 C45 C15 15 30 90 C30 0 45 60 75 temperature ( c) 3730 g12 C45 C15 15 30 90 C30 0 45 60 75 100 80 60 40 20 0 v run/ss voltage (v) 0 maximum i sense (mv) 80 70 60 50 40 30 20 10 0 4 3730 g13 1 2 3 56 v ith (v) 0 i sense voltage threshold (mv) 75 60 45 30 15 0 C15 0.6 1.2 1.8 2.4 3730 g14 percentage of nominal output voltage (%) 0 peak i sense voltage (mv) 80 70 60 50 40 30 20 10 0 80 3730 g15 20 10 30 50 70 90 40 60 100 v out (v) 0 i sense pin current ( a) 40 30 20 10 0 C10 C20 C30 3730 g17 2 5 1 34 arming latchoff v pllfltr = 0v v cc = 5v v run/ss = 1.9v duty factor (%) 0 0 i sense voltage (mv) 25 50 75 20 40 60 80 3730 g13a 100 typical perfor a ce characteristics uw short-circuit arming and latchoff vs temperature supply current vs temperature run/ss pull-up current vs temperature maximum i sense vs v run/ss peak current threshold vs v ith percentage of nominal output vs peak i sense (foldback) maximum duty factor vs temperature i sense pin current vs v out maximum current sense threshold vs duty factor
7 ltc3730 3730fa typical perfor a ce characteristics uw burst mode at 1amp, light load current (circuit of figure 14) shed mode at 1amp, light load current (circuit of figure 14) transient load current response: 0amp to 50amp (circuit of figure 14) continuous mode at 1amp, light load current (circuit of figure 14) operational amplifier gain-phase 3730 g20 3730 g22 3730 g23 3730 g21 v in = 12v v out = 1.5v v fcb = 0v frequency = 250khz v in = 12v v out = 1.5v v fcb = v cc frequency = 250khz v in = 12v v out = 1.5v v fcb = v cc frequency = 250khz v in = 12v v out = 1.5v v fcb = open frequency = 250khz v out ac, 20mv/div v sw1 10v/div v sw2 10v/div v sw3 10v/div v out ac, 20mv/div v out ac, 20mv/div i load 20a/div v sw1 10v/div v sw2 10v/div v sw3 10v/div v out ac, 20mv/div v sw1 10v/div v sw2 10v/div v sw3 10v/div 4 s/div 4 s/div 4 s/div 20 s/div frequency (khz) gain (db) 0.1 10 100 1000 3730 g19 1 60 50 40 30 20 10 0 0 C30 C60 C90 C120 C150 phase (deg) C + 100 f 100k 1k 5k in
8 ltc3730 3730fa uu u pi fu ctio s vid0 to vid4 (pins 1, 18, 19, 20, 36): output voltage programming input pins. a 3 a internal pull-up current is provided on each input pin. see table 1 for details. do not apply voltage to these pins prior to the application of voltage on the v cc pin. pllin (pin 2): synchronization input to phase detector. this pin is internally terminated to sgnd with 50k ? . the phase-locked loop will force the rising top gate signal of controller 1 to be synchronized with the rising edge of the pllin signal. pllfltr (pin 3): the phase-locked loops lowpass filter is tied to this pin. alternatively, this pin can be driven with an ac or dc voltage source to vary the frequency of the internal oscillator. (do not apply voltage to this pin prior to the application of voltage on the v cc pin.) fcb (pin 4): forced continuous control input. the voltage applied to this pin sets the operating mode of the control- ler. the forced continuous current mode is active when the applied voltage is less than 0.6v. burst mode operation will be active when the pin is allowed to float and a stage shedding mode will be active if the pin is tied to the v cc pin. (do not apply voltage to this pin prior to the application of voltage on the v cc pin.) in + , in (pins 5, 6): inputs to an operational amplifier. ampout (pin 7): output of the operational amplifier. this amplifier can be used as a switchable voltage gain ampli- fier to determine the output voltage or as a remote sensing amplifier. eain (pin 8): this is the input to the error amplifier which compares the internally vid divided output voltage to the internal 0.6v reference voltage. sgnd (pin 9): signal ground. this pin must be routed separately under the ic to the pgnd pin and then to the main ground plane. sense1 + , sense2 + , sense3 + , sense1 , sense2 , sense3 (pins 10 to 15): the inputs to each differential current comparator. the i th pin voltage and built-in offsets between sense C and sense + pins, in conjunction with r sense , set the current trip threshold level. run/ss (pin 16): combination of soft-start, run con- trol input and short-circuit detection timer. a capacitor to ground at this pin sets the ramp time to full current output as well as the time delay prior to an output voltage short-circuit shutdown. a minimum value of 0.01 f is recommended on this pin. i th (pin 17): error amplifier output and switching regu- lator compensation point. all three current comparators thresholds increase with this control voltage. pgnd (pin 26): driver power ground. this pin connects to the sources of the bottom n-channel external mosfets and the (C) terminals of c in . bg1 to bg3 (pins 27, 25, 24): high current gate drives for bottom n-channel mosfets. voltage swing at these pins is from ground to v cc . v cc (pin 28): main supply pin. because this pin supplies both the controller circuit power as well as the high power pulses supplied to drive the external mosfet gates, this pin needs to be very carefully and closely decoupled to the ics pgnd pin. sw1 to sw3 (pins 32, 29, 23): switch node connections to inductors. voltage swing at these pins is from a schot- tky diode (external) voltage drop below ground to v in (where v in is the external mosfet supply rail). tg1 to tg3 (pins 33, 30, 22): high current gate drives for top n-channel mosfets. these are the outputs of floating drivers with a voltage swing equal to the boost voltage source superimposed on the switch node voltage sw. boost1 to boost3 (pins 34, 31, 21): positive supply pins to the topside floating drivers. bootstrapped capaci- tors, charged with external schottky diodes and a boost voltage source, are connected between the boost and sw pins. voltage swing at the boost pins is from boost source voltage (typically v cc ) to this boost source voltage +v in (where v in is the external mosfet supply rail). pgood (pin 35): this open-drain output is pulled low when the output voltage has been outside the pgood tolerance window for the v uvdly delay of approximately 100 s.
9 ltc3730 3730fa fu ctio al diagra u u w switch logic clk2 clk1 sw shdn 3mv fcb top boost tg c b c in d b pgnd bot bg v cc v cc v in + v out 3730 f02 drop out det run soft- start bot force bot s r q q clk3 oscillator pllfltr 50k 0.600v 0.660v 1.5 a 6v rst shdn run/ss c ss 5(v fb ) 0.55v b 5(v fb ) 0.86v slope comp + C sense + v cc 36k 54k 54k 2.4v ss clamp i 1 sgnd 0.600v internal supply v cc c cc v cc phase det pllin duplicate for second and third controller channels + C + C r sense l c out + f in r lp c lp + C + C + C in C ampout eain v fb r1 20k ov r2 variable i th c c vid0 vid1 vid2 vid3 vid4 r c in + fcb + C C + 5-bit vid decoder + v ref v cc eain 0.66v rs latch fcb 0.6v 0.54v + C i 2 sense C 36k + C a1 ea pgood uv reset protection 100 s delay shed figure 2 operatio u (refer to functional diagram) main control loop the ic uses a constant frequency, current mode step- down architecture. during normal operation, each top mosfet is turned on each cycle when the oscillator sets the rs latch, and turned off when the main current comparator, i 1 , resets each rs latch. the peak inductor current at which i 1 resets the rs latch is controlled by the voltage on the i th pin, which is the output of the error amplifier ea. the eain pin receives a portion of this voltage feedback signal via the ampout pin through the internal vid dac and is compared to the internal reference voltage. when the load current increases, it causes a slight decrease in the eain pin voltage relative to the 0.6v reference, which in turn causes the i th voltage to increase until each inductors average current matches one third of the new load current (assuming all three current sensing resistors are equal). in burst mode operation and stage shedding mode, after each top mosfet has turned off, the bottom mosfet is turned on until either the inductor current starts to reverse, as indicated by current compara- tor i 2 , or the beginning of the next cycle.
10 ltc3730 3730fa operatio u (refer to functional diagram) results in output signals to the mosfets that turn them on for several cycles, followed by a variable sleep interval depending upon the load current. the resultant output voltage ripple is held to a very small value by having the hysteretic comparator after the error amplifier gain block. b) stage shedding operation when the fcb pin is tied to the v cc pin, burst mode operation is disabled and the forced minimum inductor current requirement is removed. this provides constant frequency, discontinuous current operation over the wid- est possible output current range. at approximately 10% of maximum designed load current, the second and third output stages are shut off and the first output stage alone is active in discontinuous current mode. this stage shedding optimizes efficiency by eliminating the gate charging losses and switching losses of the other two output stages. additional cycles will be skipped when the output load current drops below 1% of maximum de- signed load current in order to maintain the output voltage. this stage shedding operation is not as efficient as burst mode operation at very light loads, but does provide lower noise, constant frequency operating mode down to light load conditions. c) continuous current operation tying the fcb pin to ground will force continuous current operation. this is the least efficient operating mode, but may be desirable in certain applications. the output can source or sink current in this mode. when sinking current while in forced continuous operation, the controller will cause current to flow back into the input filter capacitor. if large enough, this element will prevent the input supply from boosting to unacceptably high levels; see c out selection in the applications information section. frequency synchronization the phase-locked loop allows the internal oscillator to be synchronized to an external source using the pllin pin. the output of the phase detector at the pllfltr pin is also the dc frequency control input of the oscillator, which operates over a 250khz to 600khz range corresponding to a voltage input from 0v to 2.4v. when locked, the pll the top mosfet drivers are biased from floating boot- strap capacitor c b , which is normally recharged through an external schottky diode during each off cycle. when v in decreases to a voltage close to v out , however, the loop may enter dropout and attempt to turn on the top mosfet continuously. the dropout detector counts the number of oscillator cycles that the bottom mosfet remains off and periodically forces a brief on period to allow c b to re- charge. the main control loop is shut down by pulling the run/ss pin low. releasing run/ss allows an internal 1.5 a current source to charge soft-start capacitor c ss . when c ss reaches 1.5v, the main control loop is enabled and the internally buffered i th voltage is clamped but allowed to ramp as the voltage on c ss continues to ramp. this soft- start clamping prevents abrupt current from being drawn from the input power source. when the run/ss pin is low, all functions are kept in a controlled state. the run/ss pin is pulled low when the v cc input voltage is below 4v or when the ic die temperature rises above 150 c. low current operation the fcb pin is a multifunction pin: 1) an analog compara- tor input to provide regulation for a secondary winding by forcing temporary forced pwm operation and 2) a logic input to select between three modes of operation. a) burst mode operation when the fcb pin voltage is below 0.6v, the controller performs as a continuous, pwm current mode synchro- nous switching regulator. the top and bottom mosfets are alternately turned on to maintain the output voltage independent of direction of inductor current. when the fcb pin is below v cc C 1.5v but greater than 0.6v, the controller performs as a burst mode switching regulator. burst mode operation sets a minimum output current level before turning off the top switch and turns off the synchro- nous mosfet(s) when the inductor current goes nega- tive. this combination of requirements will, at low current, force the i th pin below a voltage threshold that will temporarily shut off both output mosfets until the output voltage drops slightly. there is a burst comparator having 60mv of hysteresis tied to the i th pin. this hysteresis
11 ltc3730 3730fa operatio u (refer to functional diagram) aligns the turn on of the top mosfet to the rising edge of the synchronizing signal. when no frequency information is supplied to the pllin pin, pllfltr goes low, forcing the oscillator to minimum frequency. a dc source can be applied to the pllfltr pin to externally set the desired operating frequency. a discharge current of approxi- mately 20 a will be present at the pin with no pllin signal. input capacitance esr requirements and efficiency losses are reduced substantially in a multiphase architecture because the peak current drawn from the input capacitor is effectively divided by the number of phases used and power loss is proportional to the rms current squared. a 3-stage, single output voltage implementation can reduce input path power loss by 90%. operational amplifier this amplifier can be used to satisfy output voltage re- quirements that change according to the mode of circuit or cpu operation. the output voltage can be dropped several hundred millivolts when using an externally switched resistive divider based upon the activity level or speed requirement by changing the output voltage feedback factor. the amplifier can swing to within 1.2v of the positive power supply at low output current ( 1ma). the amplifier has an output slew rate of 5v/ s and is capable of driving capacitive loads at an output sourcing rms current of up to 10ma. power good the pgood pin is connected to the drain of an internal n-channel mosfet. the mosfet is turned on once an internal delay has elapsed and the output voltage has been away from its nominal value by greater than 10%. if the output returns to normal prior to the delay timeout, the timer is reset. there is no delay time for the rising of the pgood output once the output voltage is within the 10% window. short-circuit detection the run/ss capacitor is used initially to turn on and limit the inrush current from the input power source. once the controllers have been given time, as determined by the capacitor on the run/ss pin, to charge up the output capacitors and provide full load current, the run/ss capacitor is then used as a short-circuit timeout circuit. if the output voltage falls to less than 70% of its nominal output voltage, the run/ss capacitor begins discharging, assuming that the output is in a severe overcurrent and/or short-circuit condition. if the condition lasts for a long enough period, as determined by the size of the run/ss capacitor, the controller will be shut down until the run/ss pin voltage is recycled. this built-in latchoff can be over- ridden by providing >5 a at a compliance of 3.8v to the run/ss pin. this additional current shortens the soft- start period but prevents net discharge of the run/ss capacitor during a severe overcurrent and/or short-circuit condition. foldback current limiting is activated when the output voltage falls below 70% of its nominal level whether or not the short-circuit latchoff circuit is enabled. foldback current limit can be overridden by clamping the eain pin such that the voltage is held above the (70%)(0.6v) or 0.42v level even when the actual output voltage is low. input undervoltage reset the run/ss capacitor will be reset if the input voltage (v cc ) is allowed to fall below approximately 3.8v. the capacitor on the pin will be discharged until the short- circuit arming latch is disarmed. the run/ss capacitor will attempt to cycle through a normal soft-start ramp up after the v cc supply rises above 3.8v. this circuit prevents power supply latchoff in the event of input power switch- ing break-before-make situations. the pgood pin is held low during start-up until the run/ss capacitor rises above the short-circuit latchoff arming threshold of approxi- mately 3.8v.
12 ltc3730 3730fa applicatio s i for atio wu uu the basic application circuit is shown in figure 1 on the first page of this data sheet. external component selection is driven by the load requirement, and normally begins with the selection of an inductance value based upon the desired operating frequency, inductor current and output voltage ripple requirements. once the inductors and operating frequency have been chosen, the current sens- ing resistors can be calculated. next, the power mosfets and schottky diodes are selected. finally, c in and c out are selected according to the voltage ripple requirements. the circuit shown in figure 1 can be configured for operation up to a mosfet supply voltage of 28v (limited by the external mosfets and possibly the minimum on- time). operating frequency the ic uses a constant frequency, phase-lockable archi- tecture with the frequency determined by an internal capacitor. this capacitor is charged by a fixed current plus an additional current which is proportional to the voltage applied to the pllfltr pin. refer to the phase-locked loop and frequency synchronization section for addi- tional information. a graph for the voltage applied to the pllfltr pin versus frequency is given in figure 3. as the operating frequency is increased the gate charge losses will be higher, reducing efficiency (see efficiency considerations). the maximum switching frequency is approximately 680khz. inductor value calculation and output ripple current the operating frequency and inductor selection are inter- related in that higher operating frequencies allow the use of smaller inductor and capacitor values. so why would anyone ever choose to operate at lower frequencies with larger components? the answer is efficiency. a higher frequency generally results in lower efficiency because of mosfet gate charge and transition losses. in addition to this basic tradeoff, the effect of inductor value on ripple current and low current operation must also be consid- ered. the polyphase approach reduces both input and output ripple currents while optimizing individual output stages to run at a lower fundamental frequency, enhancing efficiency. the inductor value has a direct effect on ripple current. the inductor ripple current ? i l per individual section, n, decreases with higher inductance or frequency and in- creases with higher v in or v out : ? i v fl v v l out out in = ? ? ? ? ? ? ? 1 where f is the individual output stage operating frequency. in a polyphase converter, the net ripple current seen by the output capacitor is much smaller than the individual inductor ripple currents due to the ripple cancellation. the details on how to calculate the net output ripple current can be found in application note 77. figure 4 shows the net ripple current seen by the output capacitors for the different phase configurations. the output ripple current is plotted for a fixed output voltage as the duty factor is varied between 10% and 90% on the x-axis. the output ripple current is normalized against the inductor ripple current at zero duty factor. the graph can be used in place of tedious calculations. as shown in figure 4, the zero output ripple current is obtained when: v v k n where k n out in == 12 1 , , ..., C so the number of phases used can be selected to minimize the output ripple current and therefore the output ripple voltage at the given input and output voltages. in applica- tions having a highly varying input voltage, additional phases will produce the best results. figure 3. oscillator frequency vs v pllfltr pllfltr pin voltage (v) 0 oscillator frequency (khz) 3730 f03 700 600 500 400 300 200 0.5 1 1.5 2 2.5
13 ltc3730 3730fa accepting larger values of ? i l allows the use of low inductances but can result in higher output voltage ripple. a reasonable starting point for setting ripple current is ? i l = 0.4(i out )/n, where n is the number of channels and i out is the total load current. remember, the maximum ? i l occurs at the maximum input voltage. the individual inductor ripple currents are constant determined by the input and output voltages and the inductance. ferrite. a reasonable compromise from the same manu- facturer is kool m . toroids are very space efficient, especially when you can use several layers of wire. be- cause they lack a bobbin, mounting is more difficult. however, designs for surface mount are available which do not increase the height significantly. power mosfet and d1, d2, d3 selection at least two external power mosfets must be selected for each of the three output sections: one n-channel mosfet for the top (main) switch and one or more n-channel mosfet(s) for the bottom (synchronous) switch. the number, type and on resistance of all mosfets selected take into account the voltage step-down ratio as well as the actual position (main or synchronous) in which the mosfet will be used. a much smaller and much lower input capacitance mosfet should be used for the top mosfet in applications that have an output voltage that is less than 1/3 of the input voltage. in applications where v in >> v out , the top mosfets on resistance is normally less impor- tant for overall efficiency than its input capacitance at operating frequencies above 300khz. mosfet manufac- turers have designed special purpose devices that provide reasonably low on resistance with significantly reduced input capacitance for the main switch application in switch- ing regulators. the peak-to-peak mosfet gate drive levels are set by the voltage, v cc , requiring the use of logic-level threshold mosfets in most applications. pay close attention to the bv dss specification for the mosfets as well; many of the logic-level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on resistance r ds(on) , input capacitance, input voltage and maximum output current. mosfet input capacitance is a combination of several components but can be taken from the typical gate charge curve included on most data sheets. the curve is generated by forcing a constant input current into the gate of a common source, current source loaded stage and then plotting the gate voltage versus time. the initial slope is the effect of the gate-to-source and the gate-to-drain capacitance. the flat portion of the curve is the result of the miller multiplication effect of the drain-to-gate capacitance as the drain drops the voltage across the current source load. the upper sloping line is due to the applicatio s i for atio wu uu duty factor (v out /v in ) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 3730 f04 6-phase 4-phase 3-phase 2-phase 1-phase i o(p-p) v o /fl figure 4. normalized peak output current vs duty factor [i rms = 0.3(i o(p-p) )] inductor core selection once the value for l1 to l3 is known, the type of inductor must be selected. high efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of ferrite, molypermalloy or kool m ? cores. actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that inductance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! molypermalloy (from magnetics, inc.) is a very good, low loss core material for toroids, but it is more expensive than
14 ltc3730 3730fa drain-to-gate accumulation capacitance and the gate-to- source capacitance. the miller charge (the increase in coulombs on the horizontal axis from a to b while the curve is flat) is specified for a given v ds drain voltage, but can be adjusted for different v ds voltages by multiplying by the ratio of the application v ds to the curve specified v ds values. a way to estimate the c miller term is to take the change in gate charge from points a and b on a manufac- turers data sheet and divide by the stated v ds voltage specified. c miller is the most important selection criteria for determining the transition loss term in the top mosfet but is not directly specified on mosfet data sheets. c rss and c os are specified sometimes but definitions of these parameters are not included. where n is the number of output stages, is the tempera- ture dependency of r ds(on) , r dr is the effective top driver resistance (approximately 2 ? at v gs = v miller ), v in is the drain potential and the change in drain potential in the particular application. v th(il) is the data sheet specified typical gate threshold voltage specified in the power mosfet data sheet at the specified drain current. c miller is the calculated capacitance using the gate charge curve from the mosfet data sheet and the technique described above. both mosfets have i 2 r losses while the topside n-channel equation includes an additional term for transition losses, which peak at the highest input voltage. for v in < 12v, the high current efficiency generally improves with larger mosfets, while for v in > 12v, the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c miller actually provides higher efficiency. the synchronous mosfet losses are greatest at high input voltage when the top switch duty factor is low or during a short circuit when the synchronous switch is on close to 100% of the period. the term (1 + ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but = 0.005/ c can be used as an approximation for low voltage mosfets. the schottky diodes, (d1 to d3 in figure 1) conduct during the dead time between the conduction of the two large power mosfets. this prevents the body diode of the bottom mosfet from turning on, storing charge during the dead time and requiring a reverse recovery period which could cost as much as several percent in efficiency. a 2a to 8a schottky is generally a good compromise for both regions of operation due to the relatively small average current. larger diodes result in additional transi- tion loss due to their larger junction capacitance. c in and c out selection in continuous mode, the source current of each top n-channel mosfet is a square wave of duty cycle v out /v in . a low esr input capacitor sized for the maximum rms current must be used. the details of a close form equation can be found in application note 77. figure 6 shows the input capacitor ripple current for different phase configu- applicatio s i for atio wu uu 3730 f05 miller effect q in ab c miller = (q b C q a )/v ds v gs + C v ds v in v gs v + C figure 5 when the controller is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: main switch duty cycle v v synchronous switch duty cycle vv v out in in out in = = ? ? ? ? ? ? C the power dissipation for the main and synchronous mosfets at maximum output current are given by: p v v i n r v i n rc vv v f p vv v i n r main out in max ds on in max dr miller cc th il th il sync in out in max ds on = ? ? ? ? ? ? + () + ()( ) + ? ? ? ? ? ? ? ? () = ? ? ? ? ? ? + () 2 2 2 1 2 11 1 () () () () ? C C
15 ltc3730 3730fa rations with the output voltage fixed and input voltage varied. the input ripple current is normalized against the dc output current. the graph can be used in place of tedious calculations. the minimum input ripple current can be achieved when the product of phase number and output voltage, n(v out ), is approximately equal to the input voltage v in or: v v k n where k n out in == 12 1 , , ..., C so the phase number can be chosen to minimize the input capacitor size for the given input and output voltages. in the graph of figure 4, the local maximum input rms capacitor currents are reached when: v v k n where k n out in == 21 12 C , , ..., these worst-case conditions are commonly used for de- sign because even significant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than re- quired. several capacitors may also be paralleled to meet size or height requirements in the design. always consult the capacitor manufacturer if there is any question. the figure 6 graph shows that the peak rms input current is reduced linearly, inversely proportional to the number n of stages used. it is important to note that the efficiency loss is proportional to the input rms current squared and therefore a 3-stage implementation results in 90% less power loss when compared to a single phase design. battery/input protection fuse resistance (if used), pc board trace and connector resistance losses are also reduced by the reduction of the input ripple current in a polyphase system. the required amount of input capaci- tance is further reduced by the factor, n, due to the effective increase in the frequency of the current pulses. ceramic capacitors are becoming very popular for small designs but several cautions should be observed. x7r, x5r and y5v are examples of a few of the ceramic materials used as the dielectric layer, and these different dielectrics have very different effect on the capacitance value due to the voltage and temperature conditions applied. physically, if the capacitance value changes due to applied voltage change, there is a concommitant piezo effect which results in radiating sound! a load that draws varying current at an audible rate may cause an attendant varying input voltage on a ceramic capacitor, resulting in an audible signal. a secondary issue relates to the energy flowing back into a ceramic capacitor whose capacitance value is being reduced by the increasing charge. the voltage can increase at a considerably higher rate than the constant current being supplied because the capacitance value is decreasing as the voltage is increasing! neverthe- less, ceramic capacitors, when properly selected and used, can provide the lowest overall loss due to their extremely low esr. the selection of c out is driven by the required effective series resistance (esr). typically once the esr require- ment is satisfied the capacitance is adequate for filtering. the steady-state output ripple ( ? v out ) is determined by: ?? v i esr nfc out ripple out + ? ? ? ? ? ? 1 8 where f = operating frequency of each stage, n is the number of output stages, c out = output capacitance and ? i l = ripple current in each inductor. the output ripple is highest at maximum input voltage since ? i l increases with input voltage. the output ripple will be less than 50mv at max v in with ? i l = 0.4i out(max) assuming: applicatio s i for atio wu uu duty factor (v out /v in ) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.6 0.5 0.4 0.3 0.2 0.1 0 3730 f06 rms input ripple currnet dc load current 6-phase 4-phase 3-phase 2-phase 1-phase figure 6. normalized input rms ripple current vs duty factor for one to six output stages
16 ltc3730 3730fa c out required esr < n ? r sense and c out > 1/(8nf)(r sense ) the emergence of very low esr capacitors in small, surface mount packages makes very small physical imple- mentations possible. the ability to externally compensate the switching regulator loop using the i th pin allows a much wider selection of output capacitor types. the impedance characteristics of each capacitor type is sig- nificantly different than an ideal capacitor and therefore requires accurate modeling or bench evaluation during design. manufacturers such as nichicon, nippon chemi-con and sanyo should be considered for high performance through- hole capacitors. the os-con semiconductor dielectric capacitor available from sanyo and the panasonic sp surface mount types have a good (esr)(size) product. once the esr requirement for c out has been met, the rms current rating generally far exceeds the i ripple(p-p) requirement. ceramic capacitors from avx, taiyo yuden, murata and tokin offer high capacitance value and very low esr, especially applicable for low output voltage applications. in surface mount applications, multiple capacitors may have to be paralleled to meet the esr or rms current handling requirements of the application. aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. new special polymer surface mount capacitors offer very low esr also but have much lower capacitive density per unit volume. in the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. several excellent choices are the avx tps, avx tpsv, the kemet t510 series of sur- face-mount tantalums or the panasonic sp series of sur- face mount special polymer capacitors available in case heights ranging from 2mm to 4mm. other capacitor types include sanyo pos cap, sanyo os-con, nichicon pl series and sprague 595d series. consult the manufacturers for other specific recommendations. r sense selection for output current once the frequency and inductor have been chosen, r sense1, r sense2, r sense3 are determined based on the required peak inductor current. the current comparator has a typical maximum threshold of 75mv/r sense and an input common mode range of sgnd to (1.1) ? v cc . the current comparator threshold sets the peak inductor cur- rent, yielding a maximum average output current i max equal to the peak value less half the peak-to-peak ripple current, ? i l . allowing a margin for variations in the ic and external component values yields: rn mv i sense max = 50 the ic works well with values of r sense from 0.002 ? to 0.02 ? . v cc decoupling the v cc pin supplies power not only the internal circuits of the controller but also the top and bottom gate drivers on the ic and therefore must be bypassed very carefully to ground with a ceramic capacitor, type x7r or x5r (depending upon the operating temperature environ- ment) of at least 1 f imme diately next to the ic and preferably an additional 10 f placed very close to the ic due to the extremely high instantaneous currents in- volved. the total capacitance, taking into account the voltage coefficient of ceramic capacitors, should be 100 times as large as the total combined gate charge capaci- tance of all of the mosfets being driven. good bypass- ing close to the ic is necessary to supply the high transient currents required by the mosfet gate drivers while keep- ing the 5v supply quiet enough so as not to disturb the very small-signal high bandwidth of the current comparators. topside mosfet driver supply (c b , d b ) external bootstrap capacitors, c b , connected to the boost pins, supply the gate drive voltages for the topside mosfets. capacitor c b in the functional diagram is charged though diode d b from v cc when the sw pin is low. when one of the topside mosfets turns on, the driver places the c b voltage across the gate-source of the desired mosfet. this enhances the mosfet and turns on the topside switch. the switch node voltage, sw, rises to v in and the boost pin follows. with the topside mosfet on, the boost voltage is above the input supply (v boost = v cc + v in ). the value of the boost capacitor c b needs to be applicatio s i for atio wu uu
17 ltc3730 3730fa 30 to 100 times that of the total gate charge capacitance of the topside mosfet(s) as specified on the manufacturers data sheet. the reverse breakdown of d b must be greater than v in(max). operational amplifier the amplifier has a 0 to v cc C 1.4v common mode input range and an output swing range of 0 to v cc C 1.2v. the output uses an npn emitter follower without any internal pull-down current. a dc resistive load to ground is re- quired in order to sink current. output voltage the ic includes a digitally controlled 5-bit attenuator between the ampout pin and the eain pin resulting in output voltages as defined in table 1. output voltages with 25mv increments are produced from 0.6v to 1v and 50mv increments from 1v to 1.75v. each vid digital input is pulled up to a logical high with an internal 3 a. the input logic threshold is approximately 1.2v but the input circuit can withstand an input voltage of up to 7v. table 1. vid output voltage programming code v out code v out b4 b3 b2 b1 b0 b4 b3 b2 b1 b0 1 1111 0.600v 0 1111 1.000v 1 1110 0.625v 0 1110 1.050v 1 1101 0.650v 0 1101 1.100v 1 1100 0.675v 0 1100 1.150v 1 1011 0.700v 0 1011 1.200v 1 1010 0.725v 0 1010 1.250v 1 1001 0.750v 0 1001 1.300v 1 1000 0.775v 0 1000 1.350v 1 0111 0.800v 0 0111 1.400v 1 0110 0.825v 0 0110 1.450v 1 0101 0.850v 0 0101 1.500v 1 0100 0.875v 0 0100 1.550v 1 0011 0.900v 0 0011 1.600v 1 0010 0.925v 0 0010 1.650v 1 0001 0.950v 0 0001 1.700v 1 0000 0.975v 0 0000 1.750v soft-start/run function the run/ss pin provides three functions: 1) on/off, 2) soft-start and 3) a defeatable short-circuit latch off timer. soft-start reduces the input power sources surge cur- rents by gradually increasing the controllers current limit (proportional to an internal buffered and clamped v ith ). the latchoff timer prevents very short, extreme load transients from tripping the overcurrent latch. a small pull-up current (>5 a) supplied to the run/ss pin will prevent the overcurrent latch from operating. a maximum pull-up current of 200 a is allowed into the run/ss pin even though the voltage at the pin may exceed the absolute maximum rating for the pin. this is a result of the limited current and the internal protection circuit on the pin. the following explanation describes how this function oper- ates. an internal 1.5 a current source charges up the c ss capacitor. when the voltage on run/ss reaches 1.5v, the controller is permitted to start operating. as the voltage on run/ss increases from 1.5v to 3v, the internal current limit is increased from 0v/r sense to 75mv/r sense . the output current limit ramps up slowly, taking an additional 1s/ f to reach full current. the output current thus ramps up slowly, eliminating the starting surge current required from the input power supply. if run/ss has been pulled all the way to ground, there is a delay before starting of approximately: t v a csfc t vv a csfc delay ss ss iramp ss ss = = () = ? = () 15 15 1 315 15 1 . . / . . / by pulling the run/ss controller pin below 0.4v the ic is put into low current shutdown (i q < 50 a). the run/ss pin can be driven directly from logic as shown in figure 7. diode d1 reduces the start delay but allows c ss to ramp up slowly, providing the soft-start function. the run/ss pin has an internal 6v zener clamp (see the functional diagram). applicatio s i for atio wu uu
18 ltc3730 3730fa fault conditions: overcurrent latchoff the run/ss pins also provide the ability to latch off the controllers when an overcurrent condition is detected. the run/ss capacitor is used initially to turn on and limit the inrush current of all three output stages. after the control- lers have been started and been given adequate time to charge up the output capacitor and provide full load current, the run/ss capacitor is used for a short-circuit timer. if the output voltage falls to less than 70% of its nominal value, the run/ss capacitor begins discharging on the assumption that the output is in an overcurrent condition. if the condition lasts for a long enough period, as determined by the size of the run/ss capacitor, the discharge current, and the circuit trip point, the controller will be shut down until the run/ss pin voltage is recycled. if the overload occurs during start-up, the time can be approximated by: t lo1 >> (c ss ? 0.6v)/(1.5 a) = 4 ? 10 5 (c ss ) if the overload occurs after start-up, the voltage on the run/ss capacitor will continue charging and will provide additional time before latching off: t lo2 >> (c ss ? 3v)/(1.5 a) = 2 ? 10 6 (c ss ) this built-in overcurrent latchoff can be overridden by providing a pull-up resistor to the run/ss pin from v cc as shown in figure 7. when v cc is 5v, a 200k resistance will prevent the discharge of the run/ss capacitor during an overcurrent condition but also shortens the soft-start period, so a larger run/ss capacitor value may be required. protecting the power supply system from failure. a deci- sion can be made after the design is complete whether to rely solely on foldback current limiting or to enable the latchoff feature by removing the pull-up resistor. the value of the soft-start capacitor c ss may need to be scaled with output current, output capacitance and load current characteristics. the minimum soft-start capaci- tance is given by: c ss > (c out )(v out ) (10 C4 ) (r sense ) the minimum recommended soft-start capacitor of c ss = 0.1 f will be sufficient for most applications. current foldback in certain applications, it may be desirable to defeat the internal current foldback function. a negative impedance is experienced when powering a switching regulator. that is, the input current is higher at a lower v in and decreases as v in is increased. current foldback is de- signed to accommodate a normal, resistive load having increasing current draw with increasing voltage. the eain pin should be artificially held 70% above its nominal operating level of 0.6v, or 0.42v in order to prevent the ic from folding back the peak current level. a suggested circuit is shown in figure 8. applicatio s i for atio wu uu run/ss pin run/ss pin 5v v cc r ss c ss c ss 3730 f07 d1 shdn 3.3v or 5v shdn figure 7. run/ss pin interfacing figure 8. foldback current elimination v cc 3730 f08 calculate for 0.42v to 0.55v v cc eain q1 ltc3730 why should you defeat overcurrent latchoff? during the prototyping stage of a design, there may be a problem with noise pick-up or poor layout causing the protection circuit to latch off the controller. defeating this feature allows troubleshooting of the circuit and pc layout. the internal foldback current limiting still remains active, thereby the emitter of q1 will hold up the eain pin to a voltage in the absence of v out that will prevent the internal sensing circuitry from reducing the peak output current. remov- ing the function in this manner eliminates the external mosfets protective feature under short-circuit condi- tions. this technique will also prevent the short-circuit latchoff function from turning off the part during a short- circuit event and the peak output current will only be limited to n ? 75mv/r sense .
19 ltc3730 3730fa undervoltage reset in the event that the input power source to the ic (v cc ) drops below 3.8v, the run/ss capacitor will be dis- charged to ground. when v cc rises above 3.8v, the run/ ss capacitor will be allowed to recharge and initiate another soft-start turn-on attempt. this may be useful in applications that switch between two supplies that are not diode connected, but note that this cannot make up for the resultant interruption of the regulated output. phase-locked loop and frequency synchronization the ic has a phase-locked loop comprised of an internal voltage controlled oscillator and phase detector. this allows the top mosfet of output stage 1s turn-on to be locked to the rising edge of an external source. the frequency range of the voltage controlled oscillator is 50% around the center frequency f o . a voltage applied to the pllfltr pin of 1.2v corresponds to a frequency of approximately 400khz. the nominal operating frequency range of the ic is 225khz to 680khz. the phase detector used is an edge sensitive digital type that provides zero degrees phase shift between the exter- nal and internal oscillators. this type of phase detector will not lock the internal oscillator to harmonics of the input frequency. the pll hold-in range, ? f h , is equal to the capture range, ? f c : ? f h = ? f c = 0.5 f o the output of the phase detector is a complementary pair of current sources charging or discharging the external filter components on the pllfltr pin. a simplified block diagram is shown in figure 9. if the external frequency (f pllin ) is greater than the oscil- lator frequency, f osc , current is sourced continuously, pulling up the pllfltr pin. when the external frequency is less than f osc , current is sunk continuously, pulling down the pllfltr pin. if the external and internal fre- quencies are the same, but exhibit a phase difference, the current sources turn on for an amount of time correspond- ing to the phase difference. thus, the voltage on the pllfltr pin is adjusted until the phase and frequency of the external and internal oscillators are identical. at this stable operating point, the phase comparator output is open and the filter capacitor c lp holds the voltage. the ic pllin pin must be driven from a low impedance source such as a logic gate located close to the pin. when using multiple ics for a phase-locked system, the pllfltr pin of the master oscillator should be biased at a voltage that will guarantee the slave oscillator(s) ability to lock onto the masters frequency. a voltage of 1.7v or below applied to the master oscillators pllfltr pin is recommended in order to meet this requirement. the resultant operating frequency will be approximately 550khz for 1.7v. the loop filter components (c lp , r lp ) smooth out the current pulses from the phase detector and provide a stable input to the voltage controlled oscillator. the filter components c lp and r lp determine how fast the loop acquires lock. typically r lp =10k and c lp ranges from 0.01 f to 0.1 f. minimum on-time considerations minimum on-time, t on(min) , is the smallest time duration that the ic is capable of turning on the top mosfet. it is determined by internal timing delays and the gate charge of the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: t v vf on min out in () < () if the duty cycle falls below what can be accommodated by the minimum on-time, the ic will begin to skip every other cycle, resulting in half-frequency operation. the output voltage will continue to be regulated, but the ripple current and ripple voltage will increase. applicatio s i for atio wu uu figure 9. phase-locked loop block diagram external osc 2.4v r lp 10k c lp osc digital phase/ frequency detector phase detector/ oscillator pllin 3730 f09 pllfltr 50k
20 ltc3730 3730fa the minimum on-time for the ic is generally about 110ns. however, as the peak sense voltage decreases the mini- mum on-time gradually increases. this is of particular concern in forced continuous applications with low ripple current at light loads. if the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. if an application can operate close to the minimum on- time limit, an inductor must be chosen that is low enough in value to provide sufficient ripple amplitude to meet the minimum on-time requirement. as a general rule, keep the inductor ripple current for each channel equal to or greater than 30% of i out(max) at v in(max) . efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: %efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percentage of input power. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to ? i load ? esr, where esr is the effective series resistance of c out . ? i load also begins to charge or discharge c out , generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recovery time, v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. the availability of the i th pin not only allows optimization of control loop behavior, but also provides a dc coupled and ac filtered closed-loop response test point. the dc step, rise time and settling at this test point truly reflects the closed-loop response . assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the i th external com- ponents shown in the figure 1 circuit will provide an adequate starting point for most applications. the i th series r c -c c filter sets the dominant pole-zero loop compensation. the values can be modified slightly (from 0.2 to 5 times their suggested values) to maximize transient response once the final pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be decided upon because the various types and values determine the loop feedback factor gain and phase. an output current pulse of 20% to 80% of full load current having a rise time of <2 s will produce output voltage and i th pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. the initial output voltage step, resulting from the step change in output current, may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the i th pin signal which is in the feedback loop and is the filtered and compensated control loop response. the gain of the loop will be increased by increasing r c and the bandwidth of the loop will be increased by decreasing c c . if r c is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual over- all supply performance. a second, more severe transient is caused by switching in loads with large (>1 f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. if c load is greater than 2% of c out , the switch rise time should be controlled so that the load rise time is limited to approximately 1000 ? r sense ? c load . thus a 250 f capacitor and a 2m ? r sense resistor would require a 500 s rise time, limiting the charging current to about 1a. applicatio s i for atio wu uu
21 ltc3730 3730fa applicatio s i for atio wu uu automotive considerations: plugging into the cigarette lighter as battery-powered devices go mobile, there is a natural interest in plugging into the cigarette lighter in order to conserve or even recharge battery packs during opera- tion. but before you connect, be advised: you are plugging into the supply from hell. the main battery line in an automobile is the source of a number of nasty potential transients, including load dump, reverse battery and double battery. load dump is the result of a loose battery cable. when the cable breaks connection, the field collapse in the alternator can cause a positive spike as high as 60v which takes several hundred milliseconds to decay. reverse battery is just what it says, while double battery is a consequence of tow-truck operators finding that a 24v jump start cranks cold engines faster than 12v. the network shown in figure 10 is the most straightfor- ward approach to protect a dc/dc converter from the ravages of an automotive battery line. the series diode prevents current from flowing during reverse battery, while the transient suppressor clamps the input voltage during load dump. note that the transient suppressor should not conduct during double-battery operation, but must still clamp the input voltage below breakdown of the converter. although the ic has a maximum input voltage of 32v on the sw pins, most applications will be limited to 30v by the mosfet bv dss . voltage. apply a 400khz signal into the pllin pin or apply 1.2v to the pllfltr pin. l v fi v v v khz a v v h out out in = ? () ? ? ? ? ? ? ? = ()()() ? ? ? ? ? ? ? 1 13 400 30 15 1 13 20 068 . % . . using l = 0.6 h, a commonly available value results in 34% ripple current. the worst-case output ripple for the three stages operating in parallel will be less than 11% of the peak output current. r sense1, r sense2 and r sense3 can be calculated by using a conservative maximum sense current threshold of 65mv and taking into account half of the ripple current: r mv a sense = + ? ? ? ? ? ? = ? 65 15 1 34 2 0 0037 % . use a commonly available 0.003 ? sense resistor. next verify the minimum on-time is not violated. the minimum on-time occurs at maximum v cc : t v vf v v khz ns on min out in max () = () = () = () . 13 20 400 162 the output voltage will be set by the vid code according to table 1. the power dissipation on the topside mosfet can be estimated. using a fairchild fds6688 for example, r ds(on) = 7m ? , c miller = 15nc/15v = 1000pf. at maximum input voltage with t(estimated) = 50 c: p v v cc a pf vv v khz w main () + () ? () [] + () ()() ? ? ? ? ? ? ? ? ? ()( ) + ? ? ? ? ? ? () = 18 20 15 1 0 005 50 25 0 007 20 45 23 2 1000 1 518 1 18 400 2 2 2 2 . . . C. . . ? + ltc3730 v cc 5v v bat 12v 3730 f10 figure 10. automotive application protection design example (using three phases) as a design example, assume v cc = 5v, v in = 12v(nominal), v in = 20v(max), v out = 1.3v, i max = 45a and f = 400khz. the inductance value is chosen first based upon a 30% ripple current assumption. the highest value of ripple current in each output stage occurs at the maximum input
22 ltc3730 3730fa the worst-case power dissipation by the synchronous mosfet under normal operating conditions at elevated ambient temperature and estimated 50 c junction tem- perature rise is: p vv v aw sync = ? ()( ) ? () = 20 1 3 20 15 1 25 0 007 1 84 2 . .. . a short circuit to ground will result in a folded back current of: i mv m ns v h a sc + () ? + () ? ? ? ? ? ? ? ? = 25 23 1 2 150 20 06 75 . . with a typical value of r ds(on) and d = (0.005/ c)(50 c) = 0.25. the resulting power dissipated in the bottom mosfet is: p sync = (7.5a) 2 (1.25)(0.007 ? ) 0.5w which is less than one third of the normal, full load conditions. incidentally, since the load no longer dissi- pates any power, total system power is decreased by over 90%. therefore, the system actually cools significantly during a shorted condition! pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ic. these items are also illustrated graphically in the layout diagram of figure 12. check the following in the pc layout: 1) are the signal and power ground paths isolated? keep the sgnd at one end of a printed circuit path thus preventing mosfet currents from traveling under the ic. the ic signal ground pin should be used to hook up all control circuitry on one side of the ic, routing the copper through sgnd, under the ic covering the shadow of the package, connect- ing to the pgnd pin and then continuing on to the (C) plates of c in and c out . the v cc decoupling capacitor should be placed immediately adjacent to the ic between the v cc pin and pgnd. a 1 f ceramic capacitor of the x7r or x5r type is small enough to fit very close to the ic to minimize the ill effects of the large current pulses drawn to drive the bottom mosfets. an additional 4.7 f to 10 f of ceramic, tantalum or other very low esr capacitance is recommended in or- der to keep the internal ic supply quiet. the power ground returns to the sources of the bottom n-channel mosfets, anodes of the schottky diodes and (C) plates of c in , which should have as short lead lengths as possible. 2) does the ic in + pin connect to the (+) plates of c out ? a 30pf to 300pf feedforward capacitor between the ampout and eain pins should be placed as close as possible to the ic. 3) are the sense C and sense + printed circuit traces for each channel routed together with minimum pc trace spacing? the filter capacitors between sense + and sense C for each channel should be as close as possible to the pins of the ic. connect the sense C and sense + pins to the pads of the sense resistor as illustrated in figure 11. applicatio s i for atio wu uu figure 11. kelvin sensing r sense sense + ltc3730 1000pf inductor output capacitor sense resistor 3730 f11 sense C 4) do the (+) plates of c in connect to the drains of the topside mosfets as closely as possible? this capacitor provides the pulsed current to the mosfets. (the loop area formed by c in , topside mosfet and bottom mosfets must be minimized.) 5) keep the switching nodes, switch, boost and tg away from sensitive small-signal nodes (sense + , sense C , in + , in C , eain). ideally the switch, boost and tg printed circuit traces should be routed away and separated from the ic and the quiet side of the ic. separate the high dv/dt printed circuit traces from sensi- tive small-signal nodes with ground traces or ground planes. 6) use a low impedance source such as a logic gate to drive the pllin pin and keep the lead as short as possible.
23 ltc3730 3730fa 7) minimize trace impedances of tg, bg and sw nets. tg and sw must be routed in parallel with minimum distance. figure 12 illustrates all branch currents in a three-phase switching regulator. it becomes very clear after studying the current waveforms why it is critical to keep the high switching current paths to a small physical size. high elec- tric and magnetic fields will radiate from these loops just as radio stations transmit signals. the output capacitor ground should return to the negative terminal of the input capacitor and not share a common ground path with any switched current paths. the left half of the circuit gives rise applicatio s i for atio wu uu to the noise generated by a switching regulator. the ground terminations of the synchronous mosfets and schottky diodes should return to the bottom plate(s) of the input capacitor(s) with a short isolated pc trace since very high switched currents are present. a separate isolated path from the bottom plate(s) of the input and output capacitor(s) should be used to tie in the ic power ground pin (pgnd). this technique keeps inherent signals generated by high current pulses taking alternate current paths that have fi- nite impedances during the total period of the switching regulator. external opti-loop compensation allows over- compensation for pc layouts which are not optimized but this is not the recommended design procedure. + r in v in v out c in bold lines indicate high switching currents. keep lines to a mininmum length. + c out d3 d2 sw2 d1 l1 sw1 r sense1 l2 r sense2 l3 sw3 r sense3 3730 f12 r l figure 12
24 ltc3730 3730fa simplified visual explanation of how a 3-phase controller reduces both input and output rms ripple current the effect of multiphase power supply design significantly reduces the amount of ripple current in both the input and output capacitors. the rms input ripple current is divided by, and the effective ripple frequency is multiplied up by the number of phases used (assuming that the input voltage is greater than the number of phases used times the output voltage). the output ripple amplitude is also reduced by, and the effective ripple frequency is increased by the number of phases used. figure 13 graphically illustrates the principle. applicatio s i for atio wu uu the worst-case input rms ripple current for a single stage design peaks at twice the value of the output voltage. the worst-case input rms ripple current for a two stage design results in peaks at 1/4 and 3/4 of the input voltage, and the worst-case input rms ripple current for a three stage design results in peaks at 1/6, 1/2, and 5/6 of the input voltage. the peaks, however, are at ever decreasing levels with the addition of more phases. a higher effective duty factor results because the duty factors add as long as the currents in each stage are balanced. refer to an19 for a detailed description of how to calculate rms current for the single stage switching regulator. figure 6 illustrates the rms input current drawn from the input capacitance versus the duty cycle as determined by the ration of input and output voltage. the peak input rms current level of the single phase system is reduced by 2/3 in a 3-phase solution due to the current splitting between the three stages. the output ripple current is reduced significantly when compared to the single phase solution using the same inductance value because the v out /l discharge currents term from the stages that has their bottom mosfets on subtract current from the (v cc C v out )/l charging current resulting from the stage which has its top mosfet on. the output ripple current for a 3-phase design is: i p-p = ()( ) () > v fl dc v v out in out 13 3 C the ripple frequency is also increased by three, further reducing the required output capacitance when v cc < 3v out as illustrated in figure 6. the addition of more phases, by phase locking additional controllers, always results in no net input or output ripple at v out /v in ratios equal to the number of stages imple- mented. designing a system with multiple stages close to the v out /v in ratio will significantly reduce the ripple voltage at the input and outputs and thereby improve efficiency, physical size and heat generation of the overall switching power supply. refer to application note 77 for more information on polyphase circuits. sw v single phase triple phase i cin i cout sw1 v sw2 v sw3 v i l1 i l2 i l3 i cin i cout 3730 f13 figure 13
25 ltc3730 3730fa efficiency calculation to estimate efficiency, the dc loss terms include the input and output capacitor esr, each mosfet r ds(on) , induc- tor resistance r l , the sense resistance r sense and the forward drop of the schottky rectifier at the operating output current and temperature. typical values for the design example given previously in this data sheet are: main mosfet r ds(on) = 7m ? (9m ? at 90 c) sync mosfet r ds(on) = 7m ? (9m ? at 90 c) c inesr = 20m ? c outesr = 3m ? r l = 2.5m ? r sense = 3m ? v schottky = 0.8v at 15a (0.7v at 90 c) v out = 1.3v v in = 12v i max = 45a = 0.5%/ c n = 3 f = 400khz the main mosfet is on for the duty factor v out /v in and the synchronous mosfet is on for the rest of the period or simply (1 C v out /v in ). assuming the ripple current is small, the ac loss in the inductor can be made small if a good quality inductor is chosen. the average current, i out , is used to simplify the calaculations. the equation below is not exact but should provide a good technique for the comparison of selected components and give a result that is within 10% to 20% of the final application. determining the mosfets die temperature may require iterative calculations if one is not familiar with typical performance. a maximum operating junction temperature of 90 to 100 c for the mosfets is recommended for high reliability applications. common output path dc loss: pn i n r r c loss compath max l sense outesr ? ? ? ? ? ? + () + 2 this totals 3.375w + c outesr loss. total of all three main mosfets dc loss: pn v v i n r c loss main out in max ds on inesr = ? ? ? ? ? ? ? ? ? ? ? ? + () + 2 1 () this totals 0.87w + c inesr loss at 90 c. total of all three synchronous mosfets dc loss: pn v v i n r sync out in max ds on = ? ? ? ? ? ? ? ? ? ? ? ? + () 11 2 C () this totals 7.2w at 90 c. total of all three main mosfets ac loss: pv a pf vv v khz w main in ? + ? ? ? ? ? ? = 3 45 23 2 1000 1 518 1 18 400 6 3 2 () ()() ()( ) C. . (). this totals 1w at v in = 8v, 2.25w at v in = 12v and 6.25w at v in = 20v. applicatio s i for atio wu uu
26 ltc3730 3730fa applicatio s i for atio wu uu total of all three synchronous mosfets ac gate loss: () () ()( ) ( ) 361545 q v v fnc v v e g in dsspec in dsspec = this totals 0.08w at v cc = 8v, 0.12w at v cc = 12v and 0.19w at v cc = 20v. the bottom mosfet does not experience the miller capacitance dissipation issue that the main switch does because the bottom switch turns on when its drain is close to ground the schottky rectifier loss assuming 50ns nonoverlap time: 2 ? 3(0.7v)(15a)(50ns)(41e5) this totals 1.26w. the total output power is (1.3v)(45a) = 58.5w and the total input power is approximately 60w so the % loss of each component is as follows: main switches ac loss (v in = 12v) 2.25w 3.75% main switches dc loss 0.87w 1.5% synchronous switches ac loss 0.19w 0.3% synchronous switches dc loss 7.2w 12% power path loss 3.375w 5.6% the numbers above represent the values at v in = 12v. this simple example shows that two things can be done to improve efficiency: 1) use two mosfets on the synchro- nous side and 2) use a smaller mosfet for the main switch with smaller c miller to better balance the ac loss with the dc loss. a smaller, less expensive mosfet can actually perform better in the task of the main switch. typical applicatio u 10k 30k 5v vid1 in 1000pf 27pf s1 + s1 C s2 + s2 C s3 C s3 + vid1 pllin pllfltr fcb in + in C ampout ltc3730 eain sgnd sense1 + sense1 C sense2 + sense2 C sense3 C sense3 + run/ss i th i th vid2 vid0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 pgood boost1 tg1 sw1 boost2 tg2 sw2 v cc bg1 pgnd bg2 bg3 sw3 tg3 boost3 vid4 vid3 1000pf optional for synchronization 100pf 5v v in m1 m2 5v d1 s1 + s1 C l1 0.003 ? 0.01 f 5.1k 1.5nf 470pf 1000pf 1 f vid0 in vid3 in vid4 in 3730 ta01 v out : 0.6v to 1.75v, 45a switching frequency: 300khz c in : sanyo os-con 25sp68m c out : 270 f/2v 6 panasonic sp eeue0d271r pgood 5v 47k 1 ? 1000pf vid2 in 0.1 f 0.1 f 0.1 f v in m3 m4 d2 s2 + s2 C l2 0.003 ? v in m5 m6 d3 s3 + s3 C l3 0.003 ? 10 f 6.3v 3 c out v in 5v to 24v v out + 10 f 35v 4 c in 68 f 25v + d1 to d3: b140a diodes inc l1 to l3: sumida 1 h/20a cep125 iromc-h or 1 h/19a panasonic pcc-d126h or toko eh125c m1, m3, m5: irf7811w or fds6688 or si7860dp or hat2168h m2, m4, m6: si7856dp or hat2165h 5v 10 f figure 14. cpu application 0.6v to 1.75v, 45a power supply
27 ltc3730 3730fa u package descriptio g package 36-lead plastic ssop (5.3mm) (reference ltc dwg # 05-08-1640) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. g36 ssop 0204 0.09 C 0.25 (.0035 C .010) 0 C 8 0.55 C 0.95 (.022 C .037) 5.00 C 5.60** (.197 C .221) 7.40 C 8.20 (.291 C .323) 1234 5 6 7 8 9 10 11 12 14 15 16 17 18 13 12.50 C 13.10* (.492 C .516) 25 26 22 21 20 19 23 24 27 28 29 30 31 32 33 34 35 36 2.0 (.079) max 0.05 (.002) min 0.65 (.0256) bsc 0.22 C 0.38 (.009 C .015) typ millimeters (inches) dimensions do not include mold flash. mold flash shall not exceed .152mm (.006") per side dimensions do not include interlead flash. interlead flash shall not exceed .254mm (.010") per side * ** note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale 0.42 0.03 0.65 bsc 5.3 C 5.7 7.8 C 8.2 recommended solder pad layout 1.25 0.12
28 ltc3730 3730fa part number description comments ltc1628/ltc1628-pg/ 2-phase, dual output synchronous step-down reduces c in and c out , power good output signal, synchronizable, ltc1628-sync dc/dc controllers 3.5v v in 36v, i out up to 20a, 0.8v v out 5v ltc1629/ 20a to 200a polyphase synchronous controllers expandable from 2-phase to 12-phase, uses all ltc1629-pg surface mount components, no heat sink, v in up to 36v ltc1702a no r sense tm 2-phase dual synchronous step-down 550khz, no sense resistor controller ltc1703 no r sense 2-phase dual synchronous step-down mobile pentium ? iii processors, 550khz, controller with 5-bit mobile vid control v in 7v ltc1708-pg 2-phase, dual synchronous controller with mobile vid 3.5v v in 36v, vid sets v out1 , pgood ltc1709/ high efficiency, 2-phase synchronous step-down 1.3v v out 3.5v, current mode ensures ltc1709-8 switching regulators with 5-bit vid accurate current sharing, 3.5v v in 36v ltc1735 high efficiency synchronous step-down output fault protection, 16-pin ssop switching regulator ltc1778 no r sense current mode synchronous step-down up to 97% efficiency, 4v v in 36v, 0.8v v out (0.9)(v in ), controller i out up to 20a ltc1929/ 2-phase synchronous controllers up to 42a, uses all surface mount components, ltc1929-pg no heat sinks, 3.5v v in 36v ltc3711 no r sense current mode synchronous step-down up to 97% efficiency, ideal for pentium iii processors, controller with digital 5-bit interface 0.925v v out 2v, 4v v in 36v, i out up to 20a ltc3729 20a to 200a, 550khz polyphase synchronous controller expandable from 2-phase to 12-phase, uses all surface mount components, v in up to 36v, qfn, ssop-28 ltc3731 3-phase, synchronizable polyphase controller expanable to 12-phase, undervoltage lockout input ltc3732 3-phase, 5-bit vid 600khz synchronous buck up to 60a vrm 9.0, vid, ssop-36 no r sense is a trademark of linear technology corporation. pentium is a registered trademark of intel corporation. rd/lt 1105 rev a ? printed in usa ? linear technology corporation 2002 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com related parts typical applicatio u 4.99k 49.9k 5v vid1 in 20k 1% 1000pf s1 + s1 C s2 + s2 C s3 C s3 + vid1 pllin pllfltr fcb in + in C ampout ltc3730 eain sgnd sense1 + sense1 C sense2 + sense2 C sense3 C sense3 + i th run/ss vid2 vid0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 16 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 pgood boost1 tg1 sw1 boost2 tg2 sw2 v cc bg1 pgnd bg2 bg3 sw3 tg3 boost3 vid4 vid3 1000pf optional for synchronization 100pf 27pf 20k 1% v os C dprslpvr 1/2 si1034x dprslpvr v os C v os C si1034x 1/2 si1034x stpcpub stpcpub 5v v in m1 m2 5v d1 s1 + s1 C l1 0.003 ? 1.5nf 3k 100pf 0.01 f v ron 6.98k 24.3k 5v 1000pf 1 f vid0 in vid3 in vid4 in 3730 ta02 v out : 0.6v to 1.75v, 45a switching frequency: 300khz c in : sanyo os-con 25sp68m c out : 270 f/2v 6 panasonic sp eeue0d271r pgood 5v 47k 1 ? 1000pf vid2 in 0.1 f 0.1 f 0.1 f v in m3 m4 d2 s2 + s2 C l2 0.003 ? v in m5 m6 d3 s3 + s3 C l3 0.003 ? 10 f 6.3v 3 c out v os C v in 5v to 24v v out + 10 f 25v 5 c in 68 f 25v + d1 to d3: b140a diodes inc l1 to l3: sumida 1 h/20a cep125 iromc-h or 1 h/19a panasonic pcc-d126h or toko eh125c m1, m3, m5: si7860dp or hat2168h m2, m4, m6: si7856dp or hat2165h 5v 453k 21.5k 887k 100k 10k in C vidi gain 191k figure 15. imvp iii 0.6v to 1.75v, 45a power supply for mobile northwood cpu

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